this datasheet contains new product inform ation. anachip corp. reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. rev. 1.0 dec 16, 2004 1/10 features peel? 22cv10az -25 cmos programmable electrically erasable logic device architectural flexibility - 133 product terms x 44 input and array ultra low power operation - v cc = 5 volts 10% - icc = 10 a (typical) at standby - icc = 2 ma (typical) at 1 mhz - t pd = 25ns. cmos electrically erasable te c hn o l o gy - superior factory testing - reprogrammable in plastic package - reduces retrofit and development costs development/programmer support - third party software and programmers - anachip place development software - up to 22 inputs and 10 i/o pins - 12 possible macrocell configurations - synchronous preset, asynchronous clear - independent output enables - programmable clock source and polarity - 24-pin dip/soic/tssop and 28-pin plcc application versatility - replaces random logic - pin and jedec compatible with 22v10 - ideal for power-sensitive systems general description the peel?22cv10az is a programmable electrically erasable logic (peel?) device that provides a low power alternative to ordinary plds. the peel?22cv10az is available in 24-pin dip, soic, tssop and 28-pin plcc packages (see figure 19). a ?zero-power? (100a max. i cc ) standby mode makes the peel?22cv10az ideal for power sensitive applications such as handheld meters, portable communication equipment and lap- top computers/ peripherals. ee-reprogrammability provides the convenience of instant reprogramming for development and a reusable production inventory minimizing the impact of pro- gramming changes or errors. ee-reprogrammability also improves factory testability, thus ensuring the highest quality possible. figure 19 pin configuration the peel?22cv10az is jedec file compatible with standard 22v10 plds. eight additional configurations per macrocell (a total of 12) are also available by using the ?+? software/program- ming option (i.e., 22cv10az+ & 22cv10az++). the additional macrocell configurations allow more logic to be put into every device, potentially reducing the design's component count and lowering the power requirements even further. development and programming support for the peel?22cv10az is provided by popular third-party program- mers and development software. anachip also offers free win- place development software. figure 19 block diagram i/clk 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 i 9 i 10 i 11 gnd 12 24 vcc 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 18 i/o 17 i/o 16 i/o 15 i/o 14 i/o 13 i dip tssop plcc soic not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev . 1.0 dec 16, 2004 2/10 figure 21 peel?22cv10az logic array diagram not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev . 1.0 dec 16, 2004 3/10 function description the implements logic functions as sum-of-products expressions in a programmable-and/fixed-or logic array. user-defined functions are created by programming the connections of input signals into the array. user-configurable output structures in the form of i/o macrocells further increase logic flexibility. architecture overview the architecture is illustrated in the block diagram of figure 19. twelve dedicated inputs and 10 i/os provide up to 22 inputs and 10 outputs for creating logic functions (see figure 21). at the core of the device is a programmable electrically-erasable and array that drives a fixed or array. with this structure, the peel?22cv10az can implement up to 10 sum-of-products logic expressions. associated with each of the ten or functions is an i/o macrocell that can be independently programmed to one of four different configurations in standard 22v10 mode, or any one of 12 config- urations using the special ?plus? mode. the programmable mac- rocells allow each i/o to be used to create sequential or combinatorial logic functions of active-high or active-low polar- ity, while providing three different feedback paths into the and array. and/or logic array the programmable and array of the peel?22cv10az (shown in figure 21) is formed by input lines intersecting prod- uct terms. the input lines and product terms are used as follows: 44 input lines: ? 24 input lines carry the true and complement of the signals applied to the 12 input pins ? 20 additional lines carry the true and complement values of feedback or input signals from the 10 i/os 133 product terms: ? 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16) are used to form sum of product functions ? 10 output enable terms (one for each i/o) ? 1 global synchronous preset term ? 1 global asynchronous clear term ? 1 programmable clock term at each input-line/product-term intersection, there is an eeprom memory cell that determines whether or not there is a logical connection at that intersection. each product term is essentially a 44-input and gate. a product term that is con- nected to both the true and complement of an input signal will always be false and therefore will not affect the or function that it drives. when all the connections on a product term are opened, a ?don?t care? state exists and that term will always be true. when programming the peel?22cv10az, the device pro- grammer first performs a bulk erase to remove the previous pat- tern. the erase cycle opens every logical connection in the array. the device is configured to perform the user-defined function by programming selected connections in the and array. (note that peel? device programmers automatically program all of the connections on unused product terms so that they will have no effect on the output function). variable product term distribution the peel?22cv10az provides 120 product terms to drive the 10 or functions. these product terms are distributed among the outputs in groups of 8, 10, 12, 14, and 16 to form logical sums (see figure 21). this distribution allows optimum use of the device resources. programmable i/o macrocell the unique twelve-configuration output macrocell provides com- plete control over the architecture of each output. the ability to configure each output independently lets you to tailor the config- uration of the peel?22cv10az to the precise requirements of your design. macrocell architecture each i/o macrocell, as shown in figure 20, consists of a d-type flip-flop and two signal-select multiplexers. the configuration of the macrocell is determined by four eeprom bits that control the multiplexers. these bits determine the output polarity, output type (registered or non-registered) and input-feedback path (bidi- rectional i/o, combinatorial feedback). refer to table 1. for details. four of these macrocells duplicate the functionality of the industry-standard pal22v10. (see figure 21 and table 1.) figure 20 block diagram of the peel?22cv10a i/o macrocell not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev . 1.0 dec 16, 2004 4/10 in addition to emulating the four pal-type output structures (configurations 3, 4, 9, and 10), the macrocell provides eight additional configurations. equivalent circuits for the twelve mac- rocell configurations are illustrated in figure 22. these structures are accessed by specifying the peel?22cv10a+ or peel?22cv10a++ option when assembling the equations. figure 21 equivalent circuits for the four con- figurations of the i/o macrocell table 1. peel?22cv10a macrocell configuration bits configuration input/feedback select output select # a b output polarity each macrocell can be configured to implement active-high or active-low logic. programmable polarity eliminates the need for external inverters. output enable the output of each i/o macrocell can be enabled or disabled under the control of its associated programmable output enable product term. when the logical conditions progra mmed on the output enable term are satisfied, the output signal is propagated to the i/o pin. otherwise, the output buffer is switched into the high-impedance state. under the control of the output enable term, the i/o pin can func- tion as a dedicated input, a dedicated output, or a bi-directional i/ o. opening every connection on the output enable term will per- manently enable the output buffer and yield a dedicated output. conversely, if every connection is intact, the enable term will always be logically false and the i/o will function as a dedicated input. input/feedback select when configuring an i/o macrocell to implement a registered function (configurations 1 and 2 in figure 21), the q output of the flip-flop drives the feedback term. when configuring an i/o mac- rocell to implement a combinatorial output (configurations 3 and 4 in figure 21), the feedback term is taken from the i/o pin. in this case, the pin can be used as a dedicated input or a bi-direc- tional i/o (refer also to table 1.) programmable clock options 1 0 0 register feedback register active low a unique feature of the peel?22cv10az is a programmable clock multiplexer that allows you to select true or complement 2 1 0 active high forms of either the input pin or a product-term clock source. this 3 0 1 bi-directional i/o combinatorial active low feature can be accessed by specifying the peel?22cv10a++ option when assembling the equations. 4 active high when creating a peel? device design, the desired macrocell configuration is generally specified explicitly in the design file. when the design is assembled or compiled, the macrocell config- uration bits are defined in the last lines of the jedec program- ming file. output type the signal from the or array can be fed directly to the output pin (combinatorial function) or latched in the d-type flip-flop (regis- tered function). the d-type flip-flop latches data on the rising edge of the clock and is controlled by the global preset and clear terms. when the synchronous preset term is satisfied, the q out- put of the register is set high at the next rising edge of the clock input. satisfying the asynchronous clear sets q low, regardless of the clock state. if both terms are satisfied simultaneously, the clear will override the preset. not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev . 1.0 dec 16, 2004 5/10 figure 22 equivalent circuits for the twelve configurations of the peel?22cv10az+ i/o macrocell table 1. i/o macrocell equivalent circuits configuration # a b c d input/feedback select output select 1 0 0 1 0 active low 2 1 0 1 0 register active high 3 0 1 0 0 active low 4 1 1 0 0 bi-directional i/o combinatorial active high 5 0 0 1 1 active low 6 1 0 1 1 register active high 7 0 1 1 1 active low 8 1 1 1 1 combinatorial feedback combinatorial active high 9 0 0 0 0 active low 10 1 0 0 0 register active high 11 0 1 1 0 active low 12 1 1 1 0 register feedback combinatorial active high not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev . 1.0 dec 16, 2004 6/10 zero power feature the cmos peel?22cv10az features ?zero-power? standby operation for ultra-low power consumption. with the ?zero- power? feature, transition-detection circuitry monitors the inputs, i/os (including clk) and feedbacks. if these signals do not change for a period of time greater than approximately two t pd s, the outputs are latched in their current state and the device auto- matically powers down. when the next signal transition is detected, the device will ?wake up? for active operation until the signals stop switching long enough to trigger the next power- down. as a result of the ?zero-power? feature, significant power sav- ings can be realized for combin atorial or sequential operations when the inputs or clock change at a modest rate (see figure 23). figure 23 typical icc vs. input clock frequency for the 22cv10az. 22cv10az frequency vs. icc design security the peel?22cv10az provides a special eeprom security bit that prevents unauthorized reading or copying of designs pro- grammed into the device. the security bit is set by the pld pro- grammer, either at the conclusion of the programming cycle or as a separate step, after the device has been programmed. once the security bit is set it is impossible to verify (read) or program the peel? until the entire device has first been erased with the bulk-erase function. signature word the signature word feature allows a 64-bit code to be pro- grammed into the peel?22cv10az if the peel?22cv10az+ software option is used. the code can be read back even after the security bit has been set. the signature word can be used to identify the pattern programmed into the device or to record the design revision, etc. programming support anachip?s jedec file translator allows easy conversion of exist- ing 24 pin pld designs to the peel?22cv10az, without the 100 10 1 0.1 need for redesign. anachip supports a broad range of popular third party design entry systems, including the abel-to-peel arrays fitter software. anachip also offers (for free) its propri- etary winplace software, an easy-to-use entry level pc-based software development system. programming support includes all the popular third party pro- grammers such as bp microsystems, system general, logical devices, and numerous others. 0.01 0.001 0.001 0.01 0.1 1 10 frequency in mhz not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev . 1.0 dec 16, 2004 7/10 this device has been designed and tested for the specified operating ranges. improper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may cause permanent damage. table 1. absolute maximum ratings symbol parameter conditions rating unit v cc supply voltage relative to ground -0.5 to +7.0 v v i , v o voltage applied to any pin 2 relative to ground 1 -0.5 to v cc +0.6 v i o output current per pin (i ol , i oh ) 25 ma t st storage temperature -65 to +150 o c t lt lead temperature sold ering 10 seconds +300 o c table 2. operating range symbol parameter conditions min max unit commercial 4.75 5.25 v v cc supply voltage industrial 4.5 5.5 v commercial 0 +70 o c t a ambient temperature industrial -40 +85 o c t r clock rise time see note 3. 20 ns t f clock fall time see note 3. 20 ns t rvcc v cc rise time see note 3. 250 ms table 3. d.c. electrica l characteristics over the operating range (unless otherwise specified) symbol parameter conditions min max unit v oh output high voltage ? ttl v cc = min, i oh = -4.0 ma 2.4 v v ohc output high voltage ? cmos v cc = min, i oh = -10.0 a vcc-0.3 v v ol output low voltage ? ttl v cc = min, i ol = 16.0 ma 0.5 v v olc output low voltage ? cmos v cc = min, i ol = 10.0 a 0.15 v v ih input high voltage 2.0 v cc +0.3 v v il input low voltage -0.3 0.8 v i il input and i/o leakage current v cc = max, gnd v in v cc , i/o=high z 10 a i sc output short circuit current v cc = max, v o = 0.5v, t a = 25 o c -30 -135 ma i ccs v cc current, standby v in = 0v or v cc , all outputs disabled 4 10 (typ) 100 a i cc 10 v cc current, f=1mhz v in = 0v or v cc , all outputs disabled 4 2 (typ) 5 ma c in 7 input capacitance 6 pf c out 7 output capacitance t a = 25 o c, v cc =5.0v @ f = 1mhz 12 pf not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev . 1.0 dec 16, 2004 8/10 table 10. over the operating range 8 -25 symbol parameter min max unit t pd input 5 to non-registered output 25 ns t oe input 5 to output enable 6 25 ns t od input 5 to output disable 6 25 ns t co1 clock to output 15 ns t co2 clock to comb. output delay via internal registered feedback 35 ns t cf clock to feedback 9 ns t sc input 5 or feedback setup to clock 15 ns t hc input 5 hold after clock 0 ns t cl , t ch clock low time, clock high time 8 13 ns t cp min clock period ext (t sc + t co1 ) 30 ns f max1 internal feedback (1/t sc + t cf ) 11 41.6 mhz f max2 external feedback (1/t cp ) 11 33.3 mhz f max3 no feedback (1/t cl +t ch ) 11 38.4 mhz t aw asynchronous reset pulse width 25 ns t ap input to asynchronous reset 25 ns t ar asynchronous reset recovery time 25 ns t reset power-on reset time for registers in clear state 12 5 s switching waveforms inputs, i/o, registered feedback, synchronous preset clock asynchronous reset registered outputs combinatorial outputs notes: 1. minimum dc input is -0.5v, however, inputs may undershoot to -2.0v for peri- ods less than 20 ns. 2. v i and v o are not specified for program/verify operation. 3. test points for clock and vcc in t r and t f are referenced at the 10% and 90% levels. 4. i/o pins are 0v and v cc . 5. ?input? refers to an input pin signal. 6. t oe is measured from input transition to v ref 0.1v, t od is measured from input transition to v oh -0.1v or v ol +0.1v; v ref =v l. 7. capacitances are tested on a sample basis. 8. test conditions assume: signal transition times of 3ns or less from the 10% and 90% points, timing reference levels of 1.5v (unless otherwise specified). 9. test one output at a time for a duration of less than 1 second. 10. i cc for a typical application: this parameter is tested with the device pro- grammed as a 10-bit counter. 11. parameters are not 100% tested. specifications are based on initial character- ization and are tested after any design process modification that might affect oper- ational frequency. 12. all inputs at gnd. not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev . 1.0 dec 16, 2004 9/10 peel? device and array test loads technology r1 r2 r l v l c l cmos 480k ? 480k ? 228k ? 2.375v 33pf ttl 235 ? 159 ? 95 ? 2.02v 33pf ordering information part number speed temperature package peel22cv10azp-25 (l) 25ns commercial 24-pin plastic dip PEEL22CV10AZJ-25 (l) 25ns commercial 28-pin plcc peel22cv10azs-25 (l) 25ns commercial 24-pin soic peel22cv10azt-25 (l) 25ns commercial 24-pin tssop peel22cv10azpi-25 (l) 25ns industrial 24-pin plastic dip peel22cv10azji-25 (l) 25ns industrial 28-pin plcc peel22cv10azsi-25 (l) 25ns industrial 24-pin soic peel22cv10azti-25 (l) 25ns industrial 24-pin tssop part number peel tm 22cv10az pi-25x package p = 24-pin plastic 300 mil dip s = 24-pin soic 300 mil gullwing temperature range (blank) = commercial 0 to +70 o c speed lead free blank : normal l : lead free package j = 28-pin plastic (j) leaded chip carrier (plcc) suffix device t = 24-pin tssop 170 mil i = industrial -40 to +85 o c -25 = 25ns tpd not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
anachip corp. www.anachip.com.tw rev . 1.0 dec 16, 2004 10/10 anachip corp. head office, 2f, no. 24-2, industry e. rd. iv, science-based industrial park, hsinchu, 300, taiwan tel: +886-3-5678234 fax: +886-3-5678368 anachip usa 780 montague expressway, #201 san jose, ca 95131 tel: (408) 321-9600 fax: (408) 321-9696 email: sales_usa@anachip.com website: http://www.anachip.com ?2004 anachip corp. anachip reserves the right to make changes in specifications at any time and without notice. the information furnished by anachip in this publication is believed to be accurate and reliable. however, there is no responsibility assumed by anachip for its use nor for any infringements of patents or other rights of third parties resulting from its use. no licen se is granted under any patents or patent rights of anachip. anachip?s products are not authorized for use as critical components in life support devices or systems. marks bearing ? or ? are registered trademarks and trademarks of anachip corp. not recommended for new designs - contact factory for availability to find out if the package you need is available, contact customer service
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